**SuperH** (or **SH**) is a **32-bit** reduced instruction set computing (**RISC**) instruction set architecture (**ISA**) developed by [[Hitachi]] and currently produced by [[Renesas]]. It is implemented by **microcontrollers and microprocessors for embedded systems**.

At the time of introduction, **SuperH** was notable for having **fixed-length 16-bit instructions** in spite of its **32-bit architecture**. Using smaller instructions had consequences: the register file was smaller and instructions were generally **two-operand format**. However for the market the **SuperH** was aimed at, this was a **small price** to pay for the **improved memory and processor cache efficiency**.

Later versions of the design, starting with **SH-5**, **included both 16- and 32-bit instructions**, with the **16-bit versions mapping onto the 32-bit version** inside the **CPU**. This allowed the machine code to continue using the **shorter instructions** to **save memory**, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a **compressed instruction set** and is also **used by other** companies, the most notable example being [[ARM]] for its **Thumb instruction set**.

**As of 2015**, many of the original **patents** for the **SuperH** architecture **expired** and the **SH-2 CPU** was **reimplemented** as **open source hardware** under the name **J2**.

A **few years later**, the **SH-3 core was added to the family**; new features included another interrupt concept, a memory management unit (**MMU**), and a **modified cache concept**. These features required an extended instruction set, **adding six new instructions** for a **total of 68**. The **SH-3 was bi-endian**, running in **either big-endian or little-endian byte ordering**.

====== SH3 ======

The **SH-3** core also added a **DSP extension**, then called **SH-3-DSP**. With extended data paths for efficient **DSP processing**, special accumulators and a dedicated **MAC-type DSP engine**, this core unified the **DSP** and the **RISC processor** world. A derivative of the DSP was also used with the original **SH-2 core**.

**Between 1994 and 1996**, **35.1 million** **SuperH** devices were shipped worldwide.